module PM_Modulator
#(
    parameter BASEWIDTH = 10,
    parameter DEPTH=16,
    parameter Fmclk=65000000
)
(
    input wire signed [BASEWIDTH-1:0] i_Baseband_Signal,
    input wire [63:0] i_CarrierFreq,
    input wire [DEPTH-1:0] i_PhaseOffset,
    input wire i_clk,
    input wire i_rst,

    output wire [DEPTH-1:0] o_WaveAddr,
	input wire signed [BASEWIDTH-1:0] i_RAMData,
	output wire signed [BASEWIDTH-1:0] o_PM_Signal
);

wire signed [BASEWIDTH:0] biased_base;
wire [DEPTH-1:0] phase;
wire [DEPTH-1:0] DDS_fctrl;
wire [BASEWIDTH-1:0] pow2n;

assign biased_base=i_Baseband_Signal+(1<<(BASEWIDTH-2));
assign phase=((i_PhaseOffset*biased_base)/1024);
assign DDS_fctrl=(i_CarrierFreq << DEPTH) / Fmclk;



DirectDigitalSynthesizer 
    #(
        .DEPTH(DEPTH)
    )
    DDS_CarGen
    (
        .i_freq_ctrl(DDS_fctrl),
        .i_phas_ctrl(phase),
        .i_clk(i_clk),
        .i_rst(i_rst),
        .o_WaveAddr(o_WaveAddr)
    );

assign o_PM_Signal=i_RAMData;

endmodule